# Divide by SIMDRegister

**URL:** <https://forum.juce.com/t/divide-by-simdregister/28968>\
**Category:** General JUCE discussion\
**Created:** [August 12, 2018, 6:49pm UTC](https://forum.juce.com/t/divide-by-simdregister/28968 "2018-08-12T18:49:21Z")\
**Posts on this page:** 20\
**Page:** 1

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**Author:** ![finecutbodies](https://sea2.discourse-cdn.com/flex026/user_avatar/forum.juce.com/finecutbodies/32/26_2.png) [@finecutbodies](https://forum.juce.com/u/finecutbodies)\
**Post date:** [August 12, 2018, 6:49pm UTC](https://forum.juce.com/t/divide-by-simdregister/28968/1 "2018-08-12T18:49:21Z")

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Is there a way to divide by a SIMDRegister? Like can I calculate 1/SIMDReg somehow, or do anybody know about a good workaround?

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**Author:** ![tytel](https://sea2.discourse-cdn.com/flex026/user_avatar/forum.juce.com/tytel/32/655_2.png) [@tytel](https://forum.juce.com/u/tytel)\
**Post date:** [August 12, 2018, 6:57pm UTC](https://forum.juce.com/t/divide-by-simdregister/28968/2 "2018-08-12T18:57:24Z")

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There’s div in SSE but not in NEON so that’s probably why it’s not supported in SIMDRegister.  
If you’re only building for SSE devices than you could just put in the / operators in SIMDRegister.  
That or this will work without changing JUCE code:

```
SIMDRegister<float> quotient = _mm_div_ps(numerator.value, denominator.value);
```

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<div class="post-metadata">

**Author:** ![finecutbodies](https://sea2.discourse-cdn.com/flex026/user_avatar/forum.juce.com/finecutbodies/32/26_2.png) [@finecutbodies](https://forum.juce.com/u/finecutbodies)\
**Post date:** [August 13, 2018, 5:25am UTC](https://forum.juce.com/t/divide-by-simdregister/28968/3 "2018-08-13T05:25:16Z")

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thank you, that’s perfect and works nicely!

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**Author:** ![ncthom](https://sea2.discourse-cdn.com/flex026/user_avatar/forum.juce.com/ncthom/32/3721_2.png) [@ncthom](https://forum.juce.com/u/ncthom)\
**Post date:** [August 13, 2018, 2:09pm UTC](https://forum.juce.com/t/divide-by-simdregister/28968/4 "2018-08-13T14:09:29Z")

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Genuine question (showing my naiveté)– why can’t the `SIMDRegister` type implement a `operator/=` which when built against SSE uses `_mm_div_ps`, and when built against NEON or AVX has a workaround implementation which unpacks the register, performs the division operation for each value, packs the newly acquired values back into the register, then returns?

Obviously, I’m assuming, that would be a performance hit, but if you’re building against NEON, trying to use the SIMDRegister type, and need a `1/x` division operation, wouldn’t you have to write something just like this anyway?

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**Author:** ![holy-city](https://avatars.discourse-cdn.com/v4/letter/h/8491ac/32.png) [@holy-city](https://forum.juce.com/u/holy-city)\
**Post date:** [August 13, 2018, 8:19pm UTC](https://forum.juce.com/t/divide-by-simdregister/28968/5 "2018-08-13T20:19:22Z")

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imho the proper solution would be to support division on SSE platforms and have a compile error on NEON. Trusting a user to know and understand the differences between SIMD platforms kind of defeats the purpose of hiding it behind an API.

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**Author:** ![ncthom](https://sea2.discourse-cdn.com/flex026/user_avatar/forum.juce.com/ncthom/32/3721_2.png) [@ncthom](https://forum.juce.com/u/ncthom)\
**Post date:** [August 13, 2018, 8:31pm UTC](https://forum.juce.com/t/divide-by-simdregister/28968/6 "2018-08-13T20:31:32Z")

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That’s fair; I would support that solution.

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**Author:** ![kunz](https://avatars.discourse-cdn.com/v4/letter/k/f19dbf/32.png) [@kunz](https://forum.juce.com/u/kunz)\
**Post date:** [August 2, 2020, 8:35am UTC](https://forum.juce.com/t/divide-by-simdregister/28968/7 "2020-08-02T08:35:43Z")

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An SSE only solution is not possible anymore for us because of apples ARM switch. How can we proceed rewriting the code without that fundamental operator?

In my opinion it should be there and calculated without registers when not supported by the processor.

Any workarounds or other solutions welcome! Is it possible to calculate the division somehow different. Maybe with 1 / x operator?

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**Author:** ![kamedin](https://sea2.discourse-cdn.com/flex026/user_avatar/forum.juce.com/kamedin/32/11711_2.png) [@kamedin](https://forum.juce.com/u/kamedin)\
**Post date:** [August 2, 2020, 9:18am UTC](https://forum.juce.com/t/divide-by-simdregister/28968/8 "2020-08-02T09:18:10Z")

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A64 has FDIV and the vdiv intrinsics for floating-point.

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**Author:** ![kunz](https://avatars.discourse-cdn.com/v4/letter/k/f19dbf/32.png) [@kunz](https://forum.juce.com/u/kunz)\
**Post date:** [August 2, 2020, 9:34am UTC](https://forum.juce.com/t/divide-by-simdregister/28968/9 "2020-08-02T09:34:58Z")

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how does this help? how can i use this?

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**Author:** ![kunz](https://avatars.discourse-cdn.com/v4/letter/k/f19dbf/32.png) [@kunz](https://forum.juce.com/u/kunz)\
**Post date:** [August 2, 2020, 2:31pm UTC](https://forum.juce.com/t/divide-by-simdregister/28968/10 "2020-08-02T14:31:32Z")

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The whole SIMDRegister is useless for us without the division operator or the possibility to calculate the reciprocal (1/x) value and it looks to me that adding this feature and modifying the Module is not an easy and maintainable task.

Are there other ways to do this? For example to calculate the reciprocal with the SIMDRegister and the JUCE helper functions? Or does someone have a complete different solution that works for different CPU’s?

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<div class="post-metadata">

**Author:** ![kunz](https://avatars.discourse-cdn.com/v4/letter/k/f19dbf/32.png) [@kunz](https://forum.juce.com/u/kunz)\
**Post date:** [August 2, 2020, 2:38pm UTC](https://forum.juce.com/t/divide-by-simdregister/28968/11 "2020-08-02T14:38:48Z")

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> [@kamedin](#):
>
> A64 has FDIV and the vdiv intrinsics for floating-point.

Is this something that is already supported in most ARM CPU’s?

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**Author:** ![johngalt91](https://avatars.discourse-cdn.com/v4/letter/j/b38774/32.png) [@johngalt91](https://forum.juce.com/u/johngalt91)\
**Post date:** [August 2, 2020, 2:48pm UTC](https://forum.juce.com/t/divide-by-simdregister/28968/12 "2020-08-02T14:48:23Z")

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> [@kunz](#):
>
> Is this something that is already supported in most ARM CPU’s?

ARM’s NEON has floating point division intrinsics `vdivq_f32`  
You can look them [here](https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=div). I don’t know tho if it’s only in ARMv8 or ARMv7 also supports it

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<div class="post-metadata">

**Author:** ![kunz](https://avatars.discourse-cdn.com/v4/letter/k/f19dbf/32.png) [@kunz](https://forum.juce.com/u/kunz)\
**Post date:** [August 2, 2020, 3:29pm UTC](https://forum.juce.com/t/divide-by-simdregister/28968/13 "2020-08-02T15:29:43Z")

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> [@johngalt91](#):
>
> ARM’s NEON has floating point division intrinsics `vdivq_f32`  
> You can look them [here](https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=div). I don’t know tho if it’s only in ARMv8 or ARMv7 also supports it

Thanks for the information. 64 bit division seems to be there too. So, it looks almost all processors support this.

@t0m: Can we have the division feature for SIMDRegister? You could throw a compiler error if it’s not supported for the CPU like mentioned above.

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<div class="post-metadata">

**Author:** ![kamedin](https://sea2.discourse-cdn.com/flex026/user_avatar/forum.juce.com/kamedin/32/11711_2.png) [@kamedin](https://forum.juce.com/u/kamedin)\
**Post date:** [August 3, 2020, 12:12am UTC](https://forum.juce.com/t/divide-by-simdregister/28968/14 "2020-08-03T00:12:03Z")

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v8 only. It’s in the A64 instruction set.

> [@kunz](#):
>
> Is this something that is already supported in most ARM CPU’s?

I’d say yes, though juce\_neon\_SIMDNativeOps seems to use A32 intrinsics only. It’s weird that division is not implemented for SSE or AVX. I don’t know if the fallbacks are selected per operation or for the whole set -that may be a reason to exclude operations that some sets don’t have, like division in A32.

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<div class="post-metadata">

**Author:** ![johngalt91](https://avatars.discourse-cdn.com/v4/letter/j/b38774/32.png) [@johngalt91](https://forum.juce.com/u/johngalt91)\
**Post date:** [August 3, 2020, 1:14am UTC](https://forum.juce.com/t/divide-by-simdregister/28968/15 "2020-08-03T01:14:39Z")

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> [@kamedin](#):
>
> It’s weird that division is not implemented for SSE or AVX

Take it with a grain of salt, but I recall the reason was NEON didn’t have division by the time they implemented it, so it didn’t make any sense to implement the SIMD division’s wrapper containing only SSE/AVX intrinsics as the purpose of those is to use them and forget about which platform you are coding for.

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<div class="post-metadata">

**Author:** ![kamedin](https://sea2.discourse-cdn.com/flex026/user_avatar/forum.juce.com/kamedin/32/11711_2.png) [@kamedin](https://forum.juce.com/u/kamedin)\
**Post date:** [August 3, 2020, 2:50am UTC](https://forum.juce.com/t/divide-by-simdregister/28968/16 "2020-08-03T02:50:52Z")

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It’s clear that the NEON wrapper was made for A32, but there’s a SIMDFallbackOps struct to handle these cases. There could be a SIMDNativeOps::div that calls SIMDFallbackOps::div for NEON. Many things are available in some sets only, like fma, or 256-bit vectors.

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<div class="post-metadata">

**Author:** ![kunz](https://avatars.discourse-cdn.com/v4/letter/k/f19dbf/32.png) [@kunz](https://forum.juce.com/u/kunz)\
**Post date:** [August 3, 2020, 2:56pm UTC](https://forum.juce.com/t/divide-by-simdregister/28968/17 "2020-08-03T14:56:39Z")

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So, it’s time to add the division feature?

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<div class="post-metadata">

**Author:** ![kunz](https://avatars.discourse-cdn.com/v4/letter/k/f19dbf/32.png) [@kunz](https://forum.juce.com/u/kunz)\
**Post date:** [August 4, 2020, 7:50am UTC](https://forum.juce.com/t/divide-by-simdregister/28968/18 "2020-08-04T07:50:00Z")

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I was able to overwrite the division operator for the datatypes i needed without changing the juce library code.  
This way i can use all the features of the SIMDRegister struct and the division. I wasn’t able to test the ARM version, but we will see if it works soon 🙂

Here is the code:

```
#pragma once

#include "../JuceLibraryCode/JuceHeader.h"

using vec4 = juce::dsp::SIMDRegister<float>;
using vec2 = juce::dsp::SIMDRegister<double>;

#if defined( __i386__ ) || defined( __amd64__ ) || defined(_M_X64) || defined(_X86_) || defined(_M_IX86)
inline vec4 operator / (const vec4 &l, const vec4 &r)
{
    return _mm_div_ps(l.value, r.value);
}

inline vec2 operator / (const vec2 &l, const vec2 &r)
{
    return _mm_div_ps(l.value, r.value);
}

#elif defined(_M_ARM64) || defined ( __arm64__ ) || defined ( __aarch64__ )
inline vec4 operator / (const vec4 &l, const vec4 &r)
{
    return vdivq_f32(l.value, r.value);
}

inline vec2 operator / (const vec2 &l, const vec2 &r)
{
    return vdivq_f64(l.value, r.value);
}

#else
 #error "SIMD register support not implemented for this platform"
#endif

```

Still hope that division operator will be added some time. Any input is welcome.

edit: fixed ARM specific code

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<div class="post-metadata">

**Author:** ![kamedin](https://sea2.discourse-cdn.com/flex026/user_avatar/forum.juce.com/kamedin/32/11711_2.png) [@kamedin](https://forum.juce.com/u/kamedin)\
**Post date:** [August 4, 2020, 9:19am UTC](https://forum.juce.com/t/divide-by-simdregister/28968/19 "2020-08-04T09:19:09Z")

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I think for ARM it should be vdivq\_f32 and vdivq\_f64. Plain vdivs work on 64 bits (float32x2, float64x1). Also, they work only for A64, so

```auto
#elif defined(_M_ARM64) || defined ( __arm64__ ) || defined ( __aarch64__ )

```

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<div class="post-metadata">

**Author:** ![kunz](https://avatars.discourse-cdn.com/v4/letter/k/f19dbf/32.png) [@kunz](https://forum.juce.com/u/kunz)\
**Post date:** [August 5, 2020, 6:13am UTC](https://forum.juce.com/t/divide-by-simdregister/28968/20 "2020-08-05T06:13:40Z")

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Thanks for the fixes!

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