SIMD with four doubles?

Hi, is it possible to use a __m256d with the SIMDRegister, i.e.four doubles?
I have AVX but not AVX2 on my machine.

It looks to me like juce_avx_SIMDNativeOps (which supports __m256d) is only built if AVX2 and JUCE_USE_SIMD are enabled. If AVX2 isn’t enabled, the SSE version of SIMDNativeOps (which only supports __m128d) will be used instead.

1 Like

That’s a shame, thanks for looking that up I couldn’t work out the juce SIMD code very well.
The __m256d exists for me though. But I guess they are just structures now.

OK, I’ve decided I want to use just SSE & SSE2 in my architecture - is there anyway of disabling AVX2 for those that actually have it, so I don’t create large bit SIMDRegisters?